1. Field of the Invention
The present invention relates to a semiconductor device wherein a plurality of chips are mounted in the same package that singly constitutes a system, and to semiconductor devices mounted in the above semiconductor device. Particularly, the present invention relates to a technique for testing the memory chip(s) mounted in the above semiconductor device.
Moreover, the present invention relates to a technique for supplying a clock signal to be used in the semiconductor chips constituting the above semiconductor device.
2. Description of the Related Art
Recently there have been developed packaging techniques for providing a semiconductor device in which a memory chip, a digital chip, an analog chip, passive components and so on whose respective process techniques are different are accommodated in a single package that acts as a system. Particularly, a semiconductor device developed by use of a design circumstance including not only an LSI design process but also a mounting process in view of the affection of the wires between the chips is called System-In-Package (hereinafter referred to as SIP) or Multi-Chip-Package (hereinafter referred to as MCP).
The test of this kind of SIP is performed in a similar manner to the test of a conventional Multi-Chip-Module (MCM). For example, if an SIP is formed by mounting a memory chip and a logic chip, then the function test of the memory chip, that of the logic chip, and the test of the mutual connection between the memory and logic chips are performed after assembly of the SIP.
If the memory chip mounted in the SIP is accessed only by the logic chip, the terminals of the memory chip need not be connected to the external terminals of the SIP In such a case, the memory chip is tested via the logic chip. In such a case, however, the memory chip test is performed by setting a variety of data in the logic chip, disadvantageously resulting in a long test time. The length of the test time directly affects the manufacturing cost.
Besides, if a variety of data are set in the logic chip to thereby allow the logic chip to produce signals for accessing the memory chip, the test program used in testing memory chips separately cannot be used. The test program used in testing memory chips separately may be used, for example, in a proof test for testing a plurality of memory chips formed on a wafer.
Conventionally, in order to deal with the above problems, even in a case when the memory chip was accessed only by the logic chip, the terminals of the memory chip mounted in the SIP were connected to the external terminals of the SIP. In this way, the memory chip can be directly accessed from the SIP exterior even after assembly of the SIP, and hence the time required to test the functions of the memory chip can be reduced.
However, if the terminals of the memory chip are connected to the external terminals of the SIP, then the numbers of the terminals and wires within the SIP are increased. For example, in a case when the memory chip and logic chip are mounted on the system board, the numbers of the wires and terminals formed in the system board are increased. This disadvantageously increases the size and manufacturing cost of the SIP
Moreover, since the wires unnecessary for the normal operation (i.e., the operation of a shipped product) are connected to the memory chip, a signal delay, characteristic degradation or other problems will occur due to the extra loads.
On the other hand, a technique has been developed in which a test circuit for performing a built-in self test (BIST) is formed in the memory chip and is controlled from the logic chip, thereby allowing the memory chip to be tested even after assembly of the SIP. However, this test circuit cannot test the interface between the logic and memory chips which is used during the normal operation.